NB6N14S
3.3 V 1:4 AnyLevelt
Differential Input to LVDS
Fanout Buffer/Translator
The NB6N14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevelt differential input signals: LVPECL, CML or
LVDS. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N14S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N14S is ideal for
translating a variety of differential or single−ended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N14S is offered in a small 3 mm x 3 mm 16−QFN
package. Application notes, models, and support documentation are
available at www.onsemi.com.
The NB6N14S is a member of the ECLinPS MAXt family of high
performance products.
Features
•
•
•
•
•
•
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Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum RMS Clock Jitter
Typically 10 ps Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
VREF_AC Reference Output
TIA/EIA − 644 Compliant
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAM*
16
1
QFN−16
MN SUFFIX
CASE 485G
1
A
L
Y
W
G
NB6N
14S
ALYW G
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
Q1
Q1
IN
W
VT 50
50 W
/IN
+
Q2
Q2
RPU
EN
(LVTTL/CMOS)
D
Q
Q3
VOLTAGE (130 mV/div)
VREF_AC
Q3
Figure 1. Logic Diagram
Device DDJ = 10 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2013
September, 2013 − Rev. 8
1
Publication Order Number:
NB6N14S/D
