SN74LVC2G126
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES205C – APRIL 1999 – REVISED FEBRUARY 2000
D
D
D
D
EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Ioff Supports Partial-Power-Down Mode
Operation
Supports 5-V VCC Operation
Package Options Include Plastic Thin
Shrink Small-Outline (DCT, DCU) Packages
DCT OR DCU PACKAGE
(TOP VIEW)
1OE
1A
2Y
GND
1
8
2
7
3
6
4
5
VCC
2OE
1Y
2A
description
This dual bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the
associated output-enable (OE) input is low.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74LVC2G126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
logic symbol†
1OE
1A
2OE
2A
1
EN
2
6
1Y
7
3
5
2Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright © 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
PRODUCT PREVIEW
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
