Preliminary Datasheet
RQJ0603LGDQA
R07DS0300EJ0600
Rev.6.00
Jan 10, 2014
Silicon P Channel MOS FET
Power Switching
Features
• Low on-resistance
RDS(on) = 158 mΩ typ (VGS = –10 V, ID = –0.9 A)
• Low drive current
• High speed switching
• 4.5 V gate drive
Outline
RENESAS Package code: PLSP0003ZB-A
(Package name: MPAK)
3
D
3
G
1
1. Source
2. Gate
3. Drain
2
2
S
1
Note:
Marking is “LG”.
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body - drain diode reverse drain current
Channel dissipation
Channel temperature
Storage temperature
Symbol
VDSS
VGSS
ID
ID(Pulse) Note1
IDR
Ratings
–60
+10 / –20
–1.8
–4.5
–1.8
Unit
V
V
A
A
A
Pch Note2
Tch
Tstg
0.8
150
–55 to +150
W
°C
°C
Notes: 1. PW ≤ 10 μs, duty cycle ≤ 1%
2. When using the glass epoxy board (FR-4: 40 × 40 × 1 mm)
R07DS0300EJ0600 Rev.6.00
Jan 10, 2014
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