September 1996
BSS100 / BSS123
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored to
minimize on-state resistance, provide superior switching
performance. This product is particularly suited to low
voltage, low current applications, such as small servo
motor controls, power MOSFET gate drivers, and other
switching applications.
BSS100: 0.22A, 100V. RDS(ON) = 6Ω @ VGS = 10V.
BSS123: 0.17A, 100V. RDS(ON) = 6Ω @ VGS = 10V
High density cell design for extremely low RDS(ON).
Voltage controlled small signal switch.
Rugged and reliable.
_______________________________________________________________________________
D
G
BSS100
BSS123
Absolute Maximum Ratings
Symbol
S
TA = 25°C unless otherwise noted
Parameter
BSS100
BSS123
Units
VDSS
Drain-Source Voltage
100
V
VDGR
Drain-Gate Voltage (RGS < 20KΩ)
100
V
VGSS
Gate-Source Voltage - Continuous
± 14
V
- Non Repetitive (TP < 50 µS)
± 20
ID
Drain Current - Continuous
- Pulsed
0.22
0.17
0.9
0.68
0.63
0.36
A
PD
Total Power Dissipation @ TA = 25°C
W
TJ,TSTG
Operating and Storage Temperature Range
-55 to 150
°C
TL
Maximum Lead Temperature for Soldering
Purposes, 1/16" from Case for 10 Seconds
300
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistacne, Junction-to-Ambient
© 1997 Fairchild Semiconductor Corporation
200
350
°C/W
BSS100 Rev. F1 / BSS123 Rev. F1
