SN54/74LS290
SN54/74LS293
DECADE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS290 and SN54 / 74LS293 are high-speed 4-bit ripple type
counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS290) or divide-by-eight (LS293) section
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP)to form BCD,
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9).
•
•
•
•
•
Corner Power Pin Versions of the LS90 and LS93
Low Power Consumption . . . Typically 45 mW
High Count Rates . . . Typically 42 MHz
Choice of Counting Modes . . . BCD, Bi-Quinary, Binary
Input Clamp Diodes Limit High Speed Termination Effects
DECADE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
14
1
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
14
MR
MR
13
12
CP1
11
CP0
10
Q0
Q3
9
8
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
LS290
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
14
1
MS
2
NC
3
MS
4
Q2
5
Q1
6
NC
7
GND
VCC
14
MR
MR
Q3
12
CP0
10
Q0
13
CP1
11
9
8
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LS293
1
NC
2
NC
3
NC
4
Q2
5
Q1
6
NC
7
GND
PIN NAMES
LOADING (Note a)
HIGH
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to ÷ 2 Section.
Clock (Active LOW going edge) Input to ÷ 5 Section (LS290).
Clock (Active LOW going edge) Input to ÷ 8 Section (LS293).
Master Reset (Clear) Inputs
Master Set (Preset-9, LS290) Inputs
Output from ÷ 2 Section (Notes b & c)
Outputs from ÷ 5 & ÷ 8 Sections (Note b)
0.05 U.L.
0.05 U.L.
0.05 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
c) The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 Input of the device.
FAST AND LS TTL DATA
5-1
LOW
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
