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CY7C09089-12AC
25/0251 CY7C09089/99 CY7C09189/99 64K/128K x 8/9 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Six Flow-Through/Pipelined devices — 64K x 8/9 organizations (CY7C09089/189) — 128K x 8/9 organizations (CY7C09099/199) • Three Modes — Flow-Through • Low operating power — Active = 195 mA (typical) — Standby = 0.05 mA (typical) • Fully synchronous interface for easier operation • Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Pipelined — Burst • Pipelined output mode on both ports allows fast 100MHz cycle time • 0.35-micron CMOS for optimum speed/power • High-speed clock to data access 6.5[1]/7.5/9/12 ns (max.) • • • • • — Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP Pin-compatible and functionally equivalent to IDT70908 and IDT709089 Logic Block Diagram R/WL R/WR OEL OER CE0L CE1L 1 0 0/1 0/1 FT/PipeL [2] CE0R CE1R 1 0 1 0/1 0 0 1 0/1 8/9 FT/PipeR [2] 8/9 I/O0L–I/O7/8L I/O0R–I/O7/8R I/O Control [3] A0–A15/16L CLKL ADSL CNTENL CNTRSTL I/O Control 16/17 16/17 Counter/ Address Register Decode True Dual-Ported RAM Array Counter/ Address Register Decode [3] A0–A15/16R CLKR ADSR CNTENR CNTRSTR Notes: 1. See page 7 for Load Conditions. 2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 3. A0–A15 for 64K; and A0–A16 for 128K devices. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06039 Rev. *A Revised December 27, 2002
CYPRESS
Cypress Semiconductor
U.S.A
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