HOME在庫検索>在庫情報

部品型式

XC5204-6PQ-100C

製品説明
仕様・特性

Product Obsolete or Under Obsolescence 0 XC5200 Series Field Programmable Gate Arrays R November 5, 1998 (Version 5.2) 0 7* Product Specification Features - • Low-cost, register/latch rich, SRAM based reprogrammable architecture - 0.5µm three-layer metal CMOS process technology - 256 to 1936 logic cells (3,000 to 23,000 “gates”) - Price competitive with Gate Arrays • System Level Features - System performance beyond 50 MHz - 6 levels of interconnect hierarchy - VersaRing™ I/O Interface for pin-locking - Dedicated carry logic for high-speed arithmetic functions - Cascade chain for wide input functions - Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins - Internal 3-state bussing capability - Four dedicated low-skew clock or signal distribution nets • Versatile I/O and Packaging - Innovative VersaRing™ I/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals - Programmable output slew-rate control maximizes performance and reduces noise - Zero Flip-Flop hold time for input registers simplifies system timing - Independent Output Enables for external bussing • Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series - Over 150 device/package combinations, including advanced BGA, TQ, and VQ packaging available Fully Supported by Xilinx Development System - Automatic place and route software - Wide selection of PC and Workstation platforms - Over 100 3rd-party Alliance interfaces - Supported by shrink-wrap Foundation software Description The XC5200 Field-Programmable Gate Array Family is engineered to deliver low cost. Building on experiences gained with three previous successful SRAM FPGA families, the XC5200 family brings a robust feature set to programmable logic design. The VersaBlock™ logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-to-market. Complete support for the XC5200 family is delivered through the familiar Xilinx software environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, VHDL, and Verilog HDL synthesis. Designers utilizing logic synthesis can use their existing tools to design with the XC5200 devices. . Table 1: XC5200 Field-Programmable Gate Array Family Members Device XC5202 XC5204 XC5206 XC5210 XC5215 256 480 784 1,296 1,936 3,000 6,000 10,000 16,000 23,000 2,000 - 3,000 4,000 - 6,000 6,000 - 10,000 8x8 10 x 12 14 x 14 18 x 18 22 x 22 CLBs 64 120 196 324 484 Flip-Flops 256 480 784 1,296 1,936 I/Os 84 124 148 196 244 TBUFs per Longline 10 14 16 20 24 Logic Cells Max Logic Gates Typical Gate Range VersaBlock Array November 5, 1998 (Version 5.2) 10,000 - 16,000 15,000 - 23,000 7-83 7

ブランド

供給状況

 
Not pic File
お探しのXC5204-6PQ-100Cは、clevertechのスタッフが在庫確認を行いメールにて結果を御連絡致します。

「見積依頼」をクリックして どうぞお進み下さい。

お支払方法

宅配業者の代金引換又は商品到着後一週間以内の銀行振込となります。


お取引内容はこちら

0.0590820313