CMOS 300 MSPS Complete DDS
AD9852
FEATURES
Frequency ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interface
10 MHz serial 2-wire or 3-wire SPI-compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and on/off
output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin
frequency hold function
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciter
FUNCTIONAL BLOCK DIAGRAM
48
I
17
17
PHASE-TOAMPLITUDE
CONVERTER
SYSTEM
CLOCK
48
PHASE
ACCUMULATOR
ACC 2
MUX
48
INV
SINC
FILTER
12
DIGITAL MULTIPLIERS
12
MUX
SYSTEM
CLOCK
DEMUX
ANALOG
OUT
12
3
MUX
MUX
MUX
DELTA
FREQUENCY
RATE TIMER
2
48 SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
ANALOG
OUT
DAC RSET
12-BIT
CONTROL
DAC
14
Q
FSK/BPSK/HOLD
DATA IN
12-BIT
COSINE
DAC
MODE SELECT
SYSTEM
CLK
CLOCK
Q
D
INT
EXT
SYSTEM
CLOCK
48
48
FREQUENCY FREQUENCY
TUNING
TUNING
WORD 2
WORD 1
14
COMPARATOR
12
14
FIRST 14-BIT
PHASE/OFFSET
WORD
ANALOG
IN
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
SECOND 14-BIT
PHASE/OFFSET
WORD
CLOCK
OUT
AM
12-BIT DC
MODULATION CONTROL
PROGRAMMING REGISTERS
÷2
SYSTEM
CLOCK
AD9852
OSK
BUS
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
GND
I/O PORT BUFFERS
READ
WRITE
SERIAL/
PARALLEL
SELECT
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
+VS
8-BIT
PARALLEL
LOAD
MASTER
RESET
00634-001
DIFF/SINGLE
SELECT
REFCLK
BUFFER
DDS CORE
MUX
REFERENCE
CLOCK IN
FREQUENCY
ACCUMULATOR
ACC 1
SYSTEM CLOCK
4× TO 20×
REFCLK
MULTIPLIER
Figure 1.
Rev. E
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