®
ADSQ-1410
®
Quad 14-Bit, 10 MSPS Sampling A/D Converter
PRELIMINARY
PRODUCT OVERVIEW
The ADSQ-1410 is a quad 10MSPS sampling
A/D optimized for applications where low noise
performance and the ability to convert full-scale
step input signals at a 10 MHz conversion rate are
required. With excellent dynamic performance up
to Nyquist frequencies, the ADSQ-1410 is also an
ideal choice for multi-channel, frequency domain
applications.
This functionally complete quad A/D uses a single
rising edge triggered Start Convert signal to control
the conversion cycles of all four A/D’s. The digital
CMOS outputs are multiplexed into pairs providing
two parallel, 3-state output buses. Four indepen-
FEATURES
dent Enable Control pins offer individual output
data and overflow/underflow selection.
A 2.5V precision internal reference, along with individual analog input range selection pins, provides
ideal tracking over temperature while allowing
each channel to be independently configured for an
analog input range of ±1V to ±2.5V.
Available in both surface-mount and through-hole
packages, the ADSQ-1410 requires only ±5V for
internal analog supplies and 2V to 5V supply for logic
outputs. Typical power dissipation is 2.7 Watts.
Common applications include medical imaging,
radar, sonar, communications and instrumentation.
FUNCTIONAL BLOCK DIAGRAM
14-bit resolution; 10 MSPS sampling rate
Quad
20 Overflow_AB
Individual channel selectable ±1V to ±2.5V input
range
66 B1 (MSB) AB
+5V 4, 10, 25, 30
Individual channel offset and gain adjustment
capabilities
-5V 5, 11
65 B2 AB
+VDD 19, 22
64 B3 AB
63 B4 AB
Offset Adj A 3
62 B5 AB
52 EN A
Input A 1
Functionally complete; low cost
noise: 0.5 LSB RMS; no missing codes
Low
61 B6 AB
3-State Register
Sub-Ranging A/D
A
SGND A 2
Range A 13
60 B7 AB
59 B8 AB
58 B9 AB
Excellent dynamic performance: SNR 80db
57 B10 AB
Offset Adj B 31
Sub-Ranging A/D
B
Input B 33
to 5V CMOS logic outputs with overflow/un2V
derflow; 3-latency delays
56 B11 AB
3-State Register
55 B12 AB
SGND B 32
54 B13 AB
48 EN B
Range B 17
Rising edge-triggered; Individual channel enable
/ Hi-z outputs
53 B14 (LSB) AB
51 EN C
Offset Adj C 9
Sub-Ranging A/D
C
Input C 7
and +2VDD to +5VDD logic output supplies
±5V
21 Overflow_CD
3-State Register
47 B1 (MSB) CD
46 B2 CD
SGND C 8
66-pin SMT or TDIP package
45 B3 CD
Range C 15
44 B4 CD
Developed for image processing applications
Sub-Ranging A/D
D
Offset Adj D 26
for both time and frequency domain
Ideal
applications
43 B5 CD
3-State Register
42 B6 CD
Input D 28
41 B7 CD
49 EN D
SGND D 27
40 B8 CD
39 B9 CD
Range D 16
38 B10 CD
Timing and Control
+2.5V REF 14
50 START CONV
2.5V REF
37 B11 CD
36 B12 CD
35 B13 CD
AGND 6, 12, 24, 29
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
OGND 18, 23
•
Tel: (508) 339-3000
34 B14 (LSB) CD
•
www.datel.com
•
e-mail: help@datel.com
14 Jan 2013 MDA_ADSQ.B03 Page 1 of 11
