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XC95144-15PQG160C

製品説明
仕様・特性

Product Obsolete/Under Obsolescence 0 XC95144 In-System Programmable CPLD R DS067 (v6.0) May 17, 2013 0 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block (FB) - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3V or 5V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview. • • • • • • • • • • • Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95144 device. 600 nce orma erf igh P (480) H Typical ICC (mA) • Power Management 400 (320) wer w Po (300) Lo 200 (160) 0 50 100 Clock Frequency (MHz) DS067_01_110101 Figure 1: Typical ICC vs. Frequency for XC95144 © 1998–2009, 2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS067 (v6.0) May 17, 2013 Product Specification www.xilinx.com 1

ブランド

XILINX

会社名

Xilinx, Inc

本社国名

U.S.A

事業概要

プログラマブルロジックデバイスの開発および販売

供給状況

 
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