ESMT
M13S128324A
DDR SDRAM
1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3;4
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V
VDD = 2.5V ~ 2.7V, VDDQ = 2.5V ~ 2.7V [for speed -3.6]
Auto & Self refresh
32ms refresh period (4K cycle)
SSTL-2 I/O interface
144Ball FBGA and 100 pin LQFP package
Ordering Information:
PRODUCT NO.
MAX FREQ
VDD
PACKAGE
COMMENTS
M13S128324A -3.6BG
275MHz
2.6V
144 Ball FBGA
Pb-free
M13S128324A -4BG
250MHz
2.5V
144 Ball FBGA
Pb-free
M13S128324A -5BG
200MHz
2.5V
144 Ball FBGA
Pb-free
M13S128324A -6BG
166MHz
2.5V
144 Ball FBGA
Pb-free
M13S128324A -4LG
250MHz
2.5V
100 pin LQFP
Pb-free
M13S128324A -5LG
200MHz
2.5V
100 pin LQFP
Pb-free
M13S128324A -6LG
166MHz
2.5V
100 pin LQFP
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 2.3
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