Revised April 2002
FIN1018
3.3V LVDS 1-Bit High Speed Differential Receiver
General Description
Features
This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high
speed transfer of clock or data.
s Greater than 400Mbs data rate
The FIN1018 can be paired with its companion driver, the
FIN1017, or with any other LVDS driver.
s Fail safe protection for open-circuit, shorted and terminated conditions
s 3.3V power supply operation
s 0.4ns maximum pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
s 8-Lead SOIC and US-8 packages save space
Ordering Code:
Order Number
Package Number
Package Description
FIN1018M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
FIN1018MX
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
FIN1018K8X
MAB08A
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
Connection Diagrams
Pin Descriptions
Pin Name
Description
ROUT
RIN+
Non-inverting Driver Input
RIN−
Inverting Driver Input
VCC
8-Lead SOIC
LVTTL Data Output
Power Supply
GND
Ground
NC
No Connect
Pin Assignment for US-8 Package
Function Table
Input
Outputs
RIN+
RIN−
L
H
L
H
L
H
ROUT
Fail Safe Condition
H
H = HIGH Logic Level
L = LOW Logic Level
Fail Safe = Open, Shorted, Terminated
© 2002 Fairchild Semiconductor Corporation
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DS500502
www.fairchildsemi.com
FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver
March 2001
FIN1018
Note A: All input pulses have frequency = 10MHz, tR or tF = 1ns
Note B: CL includes all probe and fixture capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Resulting Differential
Input Voltage (mV)
Applied Voltages (V)
Resulting Common Mode
Input Voltage (V)
VIA
VIB
VID
VIC
1.25
1.15
100
1.2
1.15
1.25
−100
1.2
2.4
2.3
100
2.35
2.3
2.4
−100
2.35
0.1
0
100
0.05
0
0.1
−100
0.05
1.2
1.5
0.9
600
0.9
1.5
−600
1.2
2.4
1.8
600
2.1
1.8
2.4
−600
2.1
0.6
0
600
0.3
0
0.6
−600
0.3
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
3
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