Revised August 2003
FIN1047
3.3V LVDS 4-Bit Flow-Through
High Speed Differential Driver
General Description
Features
This quad driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed transfer of clock and data.
s Greater than 400Mbs data rate
The FIN1047 can be paired with its companion receiver,
the FIN1048, or any other LVDS receiver.
s Power-Off protection
s Flow-through pinout simplifies PCB layout
s 3.3V power supply operation
s 0.4 ns maximum differential pulse skew
s 1.7 ns maximum propagation delay
s Low power dissipation
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Pin compatible with equivalent RS-422 and LVPECL
devices
s 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
Package Number
FIN1047M
M16A
FIN1047MTC
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
Description
DIN1, DIN2, DIN3, DIN4
LVTTL Data Inputs
DOUT1+, DOUT2+, DOUT3+, DOUT4+ Non-Inverting
Driver Outputs
DOUT1−, DOUT2−, DOUT3−, DOUT4− Inverting
Driver Outputs
EN
Driver Enable Pin
EN
Inverting Driver
Enable Pin
VCC
Power Supply
GND
Ground
Truth Table
Inputs
Outputs
EN
EN
DIN
DOUT+
H
L or OPEN
H
H
L
H
L or OPEN
L
L
H
H
L or OPEN
OPEN
L
H
X
H
X
Z
Z
L or OPEN
X
X
Z
Z
H = HIGH Logic Level
X = Don’t Care
DOUT−
L = LOW Logic Level
Z = High Impedance
© 2003 Fairchild Semiconductor Corporation
DS500589
www.fairchildsemi.com
FIN1047 3.3V LVDS 4-Bit Flow-Through High Speed Differential Driver
June 2001
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
tPLHD
Parameter
Test Conditions
Differential Propagation Delay
Typ
Max
(Note 4)
Units
0.6
Differential Propagation Delay
HIGH-to-LOW
1.1
1.7
ns
0.6
LOW-to-HIGH
tPHLD
Min
1.2
1.7
ns
tTLHD
Differential Output Rise Time (20% to 80%)
RL = 100 Ω, CL = 10 pF,
0.4
1.2
ns
tTHLD
Differential Output Fall Time (80% to 20%)
See Figure 2 (Note 8), and Figure 3
0.4
1.2
ns
0.4
ns
0.3
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
tSK(LH)
Channel-to-Channel Skew
tSK(HL)
(Note 5)
tSK(PP)
Part-to-Part Skew (Note 6)
fMAX
Maximum Frequency (Note 7)
tZHD
Differential Output Enable Time from Z to HIGH
1.7
5.0
ns
tZLD
Differential Output Enable Time from Z to LOW RL = 100Ω, CL = 10 pF,
1.7
5.0
ns
tHZD
Differential Output Disable Time from HIGH to Z See Figure 4 (Note 8), and Figure 5
2.7
5.0
ns
tLZD
Differential Output Disable Time from LOW to Z
2.7
5.0
ns
CIN
Input Capacitance
4.2
pF
COUT
Output Capacitance
5.2
pF
0.05
1.0
RL = 100Ω, See Figure 6 (Note 8)
200
250
ns
MHz
Note 4: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 5: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction.
Note 6: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 7: fMAX criteria: Input tR = tF < 1ns, 0V to 3V, 50% Duty Cycle; Output VOD > 250 mv, 45% to 55% Duty Cycle; all switching in phase channels.
Note 8: Test Circuits in Figures 2, 4, 6 are simplified representations of test fixture and DUT loading.
3
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FIN1047
AC Electrical Characteristics
