Revised August 2003
FIN1048
3.3V LVDS 4-Bit Flow-Through
High Speed Differential Receiver
General Description
Features
This quad receiver is designed for high speed interconnect
utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
s Greater than 400Mbs data rate
The FIN1048 can be paired with its companion driver, the
FIN1047, or any other LVDS driver.
s Power-Off protection
s Flow-through pinout simplifies PCB layout
s 3.3V power supply operation
s 0.4ns maximum differential pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Fail safe protection for open-circuit, shorted and terminated conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Pin compatible with equivalent RS-422 and LVPECL
devices
s 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
FIN1048M
FIN1048MTC
Package Number
M16A
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
Description
ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs
RIN1+, RIN2+, RIN3+, RIN4+
Non-Inverting LVDS Inputs
RIN1−, RIN2−, RIN3−, RIN4−
Inverting LVDS Inputs
EN
Driver Enable Pin
EN
Inverting Driver Enable Pin
VCC
Power Supply
GND
Ground
Function Table
Inputs
Outputs
EN
EN
RIN+
ROUT−
ROUT
H
L or Open
H
L
H
H
L or Open
L
H
H
L or Open Fail Safe Condition
L
H
X
H
X
X
Z
L or Open
X
X
X
Z
H = HIGH Logic Level
Z = High Impedance
© 2003 Fairchild Semiconductor Corporation
DS500588
L = LOW Logic Level
X = Don’t Care
Fail Safe = Open, Shorted, Terminated
www.fairchildsemi.com
FIN1048 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
September 2001
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
(Note 3)
Units
tPLH
Propagation Delay LOW-to-HIGH
1.0
2.5
ns
tPHL
Propagation Delay HIGH-to-LOW
1.0
2.5
ns
tTLH
Output Rise Time (20% to 80%)
|VID| = 400 mV, CL = 10 pF,
0.7
1.2
ns
tTHL
Output Fall Time (80% to 20%)
RL = 1kΩ
0.7
1.2
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
See Figure 1 and Figure 2
0.4
ns
tSK(LH)
Channel-to-Channel Skew
tSK(HL)
(Note 4)
0.3
ns
tSK(PP)
Part-to-Part Skew (Note 5)
1.0
ns
fMAX
Maximum Operating Frequency
RL = 1kΩ, CL = 10 pF,
(Note 6)
see Figure 1 and Figure 2
200
375
MHz
tZH
LVTTL Output Enable Time from Z to HIGH
6.0
ns
tZL
LVTTL Output Enable Time from Z to LOW
RL = 1kΩ, CL = 10 pF,
6.0
ns
tHZ
LVTTL Output Disable Time from HIGH to Z
See Figure 3
6.0
ns
tLZ
LVTTL Output Disable Time from LOW to Z
6.0
ns
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V.
All channels switching in phase.
Note A: All differential input pulses have frequency = 10MHz, tR or tF = 1ns
Note B: CL includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
Resulting Differential Input
Resulting Common Mode Input
Voltage (mA)
Voltage (V)
VIC
VIA
VIB
VID
1.25
1.15
100
1.2
1.15
1.25
−100
1.2
2.4
2.3
100
2.35
2.3
2.4
−100
2.35
0.1
0
100
0.05
0
0.1
−100
0.05
1.2
1.5
0.9
600
0.9
1.5
−600
1.2
2.4
1.8
600
2.1
1.8
2.4
−600
2.1
0.6
0
600
0.3
0
0.6
−600
0.3
3
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FIN1048
AC Electrical Characteristics
