Revised August 2001
FIN1531
5V LVDS 4-Bit High Speed Differential Driver
General Description
This quad driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates 5V TTL/CMOS signal levels to
LVDS levels with a typical differential output swing of 350
mV which provides low EMI at ultra low power dissipation
even at high frequencies. This device is ideal for high
speed transfer of clock and data.
The FIN1531 can be paired with its companion receiver,
the FIN1532, or with any other Fairchild LVDS receiver.
Features
s Greater than 400Mbs data rate
s 5V power supply operation
s 400ps max differential pulse skew
s 2.0ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Pin compatible with equivalent RS-422 and
PECL devices
s 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
Package Number
FIN1531M
M16A
FIN1531MTC
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Connection Diagram
Input
Outputs
EN
EN
DIN
DOUT+
H
X
H
H
L
H
X
L
L
H
H
X
OPEN
L
H
X
L
H
H
L
X
L
L
L
H
X
L
OPEN
L
H
L
H
X
Z
Z
H = HIGH Logic Level
X = Don’t Care
DOUT−
L = LOW Logic Level
Z = High Impedance
Pin Descriptions
Pin Name
DIN1, DIN2, DIN3, DIN4
Description
5V TTL/CMOS Data Input
DOUT1+, DOUT2+, DOUT3+, DOUT4+ Non-inverting LVDS Output
DOUT1−, DOUT2−, DOUT3−, DOUT4− Inverting LVDS Output
EN
Driver Enable Pin
EN
Inverting Driver Enable Pin
VCC
© 2001 Fairchild Semiconductor Corporation
Power Supply
GND
Ground
DS500505
www.fairchildsemi.com
FIN1531 5V LVDS 4-Bit High Speed Differential Driver
August 2001
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
tPLHD
Parameter
Test Conditions
Differential Propagation Delay
Differential Propagation Delay
HIGH-to-LOW
Typ
Max
(Note 3)
Units
0.5
LOW-to-HIGH
tPHLD
Min
RL = 100 Ω, CL = 10 pF,
1.4
2.0
ns
0.5
1.4
2.0
ns
tTLHD
Differential Output Rise Time (20% to 80%) See Figure 2 and Figure 3 (Note 7)
0.6
0.8
1.2
ns
tTHLD
Differential Output Fall Time (80% to 20%)
0.6
0.8
1.2
ns
0.4
ns
0.3
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
tSK(LH),
Channel-to-Channel Skew
tSK(HL)
(Note 4)
tSK(PP)
Part-to-Part Skew (Note 5)
fMAX
Maximum Frequency(Note 6)
tZHD
LVTTL Output Enable Time from Z to HIGH RL = 100Ω, CL = 10 pF,
5.0
ns
tZLD
LVTTL Output Enable Time from Z to LOW See Figure 4 and Figure 5 (Note 7)
5.0
ns
tHZD
LVTTL Output Disable Time from HIGH to Z
5.0
ns
tLZD
LVTTL Output Disable Time from LOW to Z
5.0
ns
1.0
200
250
ns
ns
Note 3: All typical values are at TA = 25°C and with VCC = 5V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, 0V to 3V, 50% Duty Cycle; Output VOD > 250 mV, 45% to 55% Duty Cycle; all output channels switching in phase.
Note 7: Test Circuits in Figure 2 and Figure 4 are simplified representations of test fixture and DUT loading.
3
www.fairchildsemi.com
FIN1531
AC Electrical Characteristics
