Revised December 2001
FIN1532
5V LVDS 4-Bit High Speed Differential Receiver
General Description
Features
This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high
speed transfer of clock and data.
s Greater than 400Mbs data rate
The FIN1532 can be paired with its companion driver, the
FIN1531, or any other LVDS driver.
s Fail safe protection for open-circuit, shorted and terminated receiver inputs
s 5V power supply operation
s 0.5 ns maximum differential pulse skew
s 3 ns maximum propagation delay
s Low power dissipation
s Power-Off protection for inputs and outputs
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Pin compatible with equivalent RS-422
and PECL devices
s 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number
Package Number
FIN1532M
M16A
FIN1532MTC
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Connection Diagram
Pin Name
Description
ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs
RIN1+, RIN2+, RIN3+, RIN4+
Non-inverting LVDS Inputs
RIN1−, RIN2−, RIN3−, RIN4−
Inverting LVDS Inputs
EN
Driver Enable Pin
EN
Inverting Driver Enable Pin
VCC
Power Supply
GND
Ground
Function Table
Input
Outputs
EN
EN
RIN+
RIN+
ROUT
H
X
H
L
H
H
X
L
H
H
X
X
L
H
L
X
L
L
H
X
L
L
H
H = HIGH Logic Level
Z = High Impedance
L
Fail Safe Condition
Top View
H
H
L
Fail Safe Condition
H
X
Z
L = LOW Logic Level
X = Don’t Care
Fail Safe = Open, Shorted, Terminated
© 2001 Fairchild Semiconductor Corporation
DS500504
www.fairchildsemi.com
FIN1532 5V LVDS 4-Bit High Speed Differential Receiver
December 2001
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
tPLH
Parameter
Test Conditions
Propagation Delay
Typ
Max
(Note 3)
Units
1.0
LOW-to-HIGH
tPHL
Min
Propagation Delay
2.0
3.0
ns
1.0
2.0
3.0
ns
HIGH-to-LOW
|VID| = 400 mV, CL = 10 pF, RL = 1kΩ
tTLH
Output Rise Time (20% to 80%)
See Figure 1 and Figure 2
tTHL
Output Fall Time (80% to 20%)
1.1
tSK(P)
Pulse Skew |tPLH - tPHL|
0.2
0.5
tSK(LH),
Channel-to-Channel Skew
0.1
0.3
ns
1.0
ns
tSK(HL)
(Note 4)
tSK(PP)
Part-to-Part Skew (Note 5)
fMAX
Maximum Operating Frequency
RL = 1kΩ, CL = 10 pF,
(Note 6)
See Figure 1 and Figure 2
1.3
200
ns
ns
260
ns
MHz
tZH
LVTTL Output Enable Time from Z to HIGH RL = 1kΩ, CL = 10 pF,
8
12.0
ns
tZL
LVTTL Output Enable Time from Z to LOW See Figure 3 and Figure 4
8
12.0
ns
tHZ
LVTTL Output Disable Time from HIGH to Z
4
8.0
ns
tLZ
LVTTL Output Disable Time from LOW to Z
4
8.0
ns
Note 3: All typical values are at TA = 25°C and with VCC = 5V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V.
All channels switching in phase.
Note A: All input pulses have frequency = 10 MHz, tR or tF = 1 ns
Note B: CL includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay
3
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FIN1532
AC Electrical Characteristics
