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STK14C88-N45I

製品説明
仕様・特性

STK14C88 32K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM FEATURES DESCRIPTION • 25ns, 35ns and 45ns Access Times • “Hands-off” Automatic STORE with External 68µF Capacitor on Power Down • STORE to nonvolatile elements Initiated by Hardware, Software or AutoStore™ • RECALL to SRAM Initiated by Software or Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to nonvolatile elements (Commercial/Industrial) • 100-Year Data Retention in nonvolatile elements (Commercial/Industrial) • Single 5V + 10% Operation • Commercial, Industrial and Military Temperatures • 32-Pin SOIC, DIP and LCC Packages The Simtek STK14C88 is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent, nonvolatile data resides in the nonvolatile elements. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) can take place automatically on power down. A 68µF or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power-down slew rate or loss of power from “hot swapping”. Transfers from the nonvolatile elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be software controlled by entering specific read sequences. A hardware STORE may be initiated with the HSB pin. BLOCK DIAGRAM PIN CONFIGURATIONS VCCX DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 INPUT BUFFERS A5 A6 A7 A8 A9 A11 A12 A13 A14 ROW DECODER Quantum Trap 512 x 512 VCAP A14 A12 A7 A6 A5 A4 A3 NC A2 A1 A0 DQ0 DQ1 DQ2 VSS VCAP POWER CONTROL STORE STATIC RAM ARRAY 512 x 512 RECALL STORE/ RECALL CONTROL HSB 32 - LCC SOFTWARE DETECT COLUMN I/O A0 - A13 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCCX HSB W A13 A8 A9 A11 G NC A10 E DQ7 DQ6 DQ5 DQ4 DQ3 32 - DIP 32 - SOIC PIN NAMES A0 - A14 E W September 2003 1 Chip Enable W Write Enable G Output Enable HSB Hardware Store Busy (I/O) VCCX Power (+ 5V) VCAP Capacitor VSS G Data In/Out E A0 A1 A2 A3 A4 A10 Address Inputs DQ0 -DQ7 COLUMN DEC Ground Document Control # ML0014 rev 0.1

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