74LCX126
Low Voltage Quad Buffer with 5V Tolerant
Inputs and Outputs
Features
General Description
■ 5V tolerant inputs and outputs
The LCX126 contains four independent non-inverting
buffers with 3-STATE outputs. Each output is disabled
when the associated output-enable (OE) input is LOW.
The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.
■ 2.3V–3.6V VCC specifications provided
■ 5.5ns tPD max. (VCC = 3.3V), 10µA ICC max.
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal(1)
■ ±24mA output drive (VCC = 3.0V)
■ Implements proprietary noise/EMI reduction circuitry
The 74LCX126 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining CMOS low power dissipation.
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
– Human body model > 2000V
– Machine model > 100V
■ Leadless DQFN package
Note:
1. To ensure the high-impedance state during power up
or down, OE should be tied to VCC through a pull-up
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Ordering Information
Order Number
Package
Number
Package Description
74LCX126M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX126SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX126BQX(2)
MLP14A
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX126MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2000 Fairchild Semiconductor Corporation
74LCX126 Rev. 1.5.1
www.fairchildsemi.com
74LCX126 — Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
December 2013
