Ultra37000 CPLD Family
5 V and 3.3 V ISR™
High Performance CPLDs
5 V and 3.3 V ISR™ High Performance CPLDs
General Description
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In-System Reprogrammable™ (ISR™) CMOS CPLDs
❐ JTAG interface for reconfigurability
❐ Design changes do not cause pinout changes
❐ Design changes do not cause timing changes
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High Density
❐ 32 to 512 macrocells
❐ 32 to 264 I/O pins
❐ 5 dedicated inputs including 4 clock pins
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Simple Timing Model
❐ No fanout delays
❐ No expander delays
❐ No dedicated vs. I/O pin delays
❐ No additional delay through PIM
❐ No penalty for using full 16 product terms
❐ No delay for steering or sharing product terms
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3.3 V and 5 V Versions
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PCI Compatible [1]
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Programmable Bus-hold Capabilities on All I/Os
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Intelligent Product Term Allocator Provides
❐ 0 to 16 product terms to any macrocell
❐ Product term steering on an individual basis
❐ Product term sharing among local macrocells
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Flexible Clocking
❐ 4 synchronous clocks per device
❐ Product term clocking
❐ Clock polarity control per logic block
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Consistent Package and Pinout Offering across All Densities
❐ Simplifies design migration
❐ Same pinout for 3.3 V and 5 V devices
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Packages
❐ 44 to 256 pins in PLCC, PQFP, TQFP, and Fine-Pitch BGA
Packages
❐ Pb-free packages available
The Ultra37000™ family of CMOS CPLDs provides a range of
high density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to bring
the flexibility, ease of use, and performance of the 22 V10 to high
density CPLDs. The architecture is based on a number of logic
blocks that are connected by a Programmable Interconnect
Matrix (PIM). Each logic block features its own product term
array, product term allocator, and 16 macrocells. The PIM
distributes signals from the logic block outputs and all input pins
to the logic block inputs.
All the Ultra37000 devices are electrically erasable and
In-System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-compliant
serial interface. Data is shifted in and out through the TDI and
TDO pins, respectively. Because of the superior routability and
simple timing model of the Ultra37000 devices, ISR allows users
to change existing logic designs while simultaneously fixing
pinout assignments and maintaining system performance.
The entire family features JTAG for ISR and boundary scan, and
is compatible with the PCI Local Bus specification, meeting the
electrical and timing requirements. The Ultra37000 family
features user programmable bus-hold capabilities on all I/Os.
Ultra37000 5 V Devices
The Ultra37000 devices operate with a 5 V supply and can
support 5 V or 3.3 V I/O levels. VCCO connections provide the
capability of interfacing to either a 5 V or 3.3 V bus. By
connecting the VCCO pins to 5 V the user insures 5V TTL levels
on the outputs. If VCCO is connected to 3.3 V the output levels
meet 3.3 V JEDEC standard CMOS levels and are 5 V tolerant.
These devices require 5 V ISR programming.
Ultra37000V 3.3 V Devices
Devices operating with a 3.3 V supply require 3.3 V on all VCCO
pins, reducing the device’s power consumption. These devices
support 3.3 V JEDEC standard CMOS output levels, and are
5V-tolerant. These devices allow 3.3 V ISR programming.
Note
1. Due to the 5 V tolerant nature of 3.3 V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2 V.
Cypress Semiconductor Corporation
Document Number: 38-03007 Rev. *I
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198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised August 23, 2012
"Not Recommended for New Design"
Features
