DATA SHEET
MOS INTEGRATED CIRCUIT
μPD45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
Description
EO
The μPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as
2,097,152 × 16 × 4 (word × bit × bank).
The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAM is compatible with Low Voltage TTL (LVTTL).
This product is packaged in 54-pin TSOP (II).
L
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
Pr
• Quad internal banks controlled by BA0(A13) and BA1(A12)
• Byte control by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
od
• CBR (Auto) refresh and self refresh
• Burst termination by Burst stop command and Precharge command
t
uc
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0344N10 (Ver.1.0)
Date Published February 2003 (K) Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2003
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
