HD74LS138
3-Line-to-8-Line Decoders / Demultiplexers
REJ03D0434–0300
Rev.3.00
Jul.13.2005
The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three
enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS138P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
-
HD74LS138FPEL
SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
EL (2,000 pcs/reel)
PRSP0016DG-A
RP
(FP-16DNV)
Note: Please consult the sales office for the above package availability.
HD74LS138RPEL
SOP-16 pin (JEDEC)
EL (2,500 pcs/reel)
Pin Arrangement
A
1
16
VCC
A
Select
Inputs
B
2
B
Y0
15
Y0
C
3
C
Y1
14
Y1
G2A
4
G2A
Y2
13
Y2
G2B
5
G2B
Y3
12
Y3
G1
6
G1
Y4
11
Y4
Outputs Y7
7
Y7
Y5
10
Y5
GND
8
9
Y6
Enable
Inputs
Y6
(Top view)
Rev.3.00, Jul.13.2005, page 1 of 7
Outputs