QSpan II™ PowerQUICC-to-PCI
Bridge Product Brief
®
Device Overview
Features
The IDT QSpan II is a PCI-to-Host processor bridge for the Freescale
PowerQUICC (MPC860/850/821), the QUICC (MC68360), and the
MC68040. It has a growing customer list of tier-one communications
vendors.
The QSpan II operates at speeds up to 50 MHz on the Host processor
bus, with programmable parity and burst/prefetch capability. Its 32-bit/
33 MHz PCI 2.2 support is ideal for embedded processor applications.
Another key feature of the QSpan II is its integrated PCI bus arbiter. This
arbiter supports up to seven external bus masters and uses a fairness
algorithm to prevent deadlocks on the bus.
Block Diagram
Hot Swap Friendly
Four FIFO Messaging
Hot Swap
Controller
I2 0
QBus Slave Channel
Posted Writes, Prefetched Reads,
Delayed Single Reads/Writes
PCI/QBus Interrupts,
Mailbox Registers
32-bit Address and Data
50 MHz Processor Bus
Interrupt Channel
QBus (Processor) Interface
FIFO-based,
Direct/Linked List Mode
PCI Interface
32-bit Address and Data
33 MHz PCI Bus
IDMA/DMA Channel
Posted Writes, Prefetched Reads,
Delayed Single Reads/Writes
Typical Applications
JTAG
8091862_BK001_03
Up to 7 External
Bus Masters
Benefits
• Industry-proven PCI System Interconnect device
• Reduces customer’s design hours and time-to-market using
QSpan II’s design support tools
PCI Target Channel
PCI Bus
Arbiter
• Integrated PCI Bus Arbiter
– Supports up to seven external bus masters
– Fairness algorithm for preventing deadlocks
• CompactPCI Hot Swap Friendly
• High-performance DMA controller with support for Direct and
Linked List modes
• Mailbox registers for passing parameters between host and
embedded environments
• PCI version 2.2 Enhancements
– Vital Product Data: offers an improved method of communicating board-specific information to the system
– PCI Power Management interface: enables operating systems
to control the power supplied to QSpan II related hardware (for
example, an add-in card)
• High-Performance PCI Bus Interface
– Zero-wait state bursts, prefetch reads and writes on PCI
– Serial EEPROM interface for Plug and Play compatibility on
PCI
– Universal PCI signaling (3.3 and 5V compliant)
• High-Performance Processor Interface
– MPC860 interface supports prefetched reads and burst writes
– Operates up to 50 MHz
IEEE1149.1 Boundary Scan
The QSpan II also has a DMA controller for reliable, high-performance
data transfer between the PCI bus and the Host processor bus. Two
modes of DMA operation (Direct and Linked List) offer designers a
greater level of flexibility.
The QSpan II further distinguishes itself by providing embedded
systems designers access to CompactPCI Hot Swap, PCI v2.2 Vital
Product Data (VPD), Power Management, and four, 32-bit mailbox registers.
QSpan II’s typical applications include the following:
• LAN/WAN Infrastructure
– Network interface cards
– Routers (including SOHO applications)
– Servers
• Remote and Local Access Equipment
– xDSL concentrators
– VoIP gateways
• CPE Equipment
– Process control equipment
– Data acquisition systems
The device is offered in two packages: a 17 x 17 mm package with a
1.0 mm ball pitch, and a 27 x 27 mm package with a 1.27 mm ball pitch.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2009 Integrated Device Technology, Inc.
October 26, 2009
