TSB12LV32
TSB12LV32I
www.ti.com
SLLA215 – JUNE 2006
IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller for
Computer Peripherals and Consumer Audio/Video Electronics
FEATURES
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Compliant With IEEE 1394-1995 Standards
and 1394a-2000 Supplement for High
Performance Serial Bus1
Supports Transfer Rates of 400, 200, or 100
Mbps
Compatible With Texas Instruments Physical
Layer Controllers (Phys)
Supports the Texas Instruments Bus Holder
Galvanic Isolation Barrier
Glueless Interface to 68000 and ColdFire
Microcontrollers/Microprocessors
Supports ColdFire Burst Transfers
2-Kbyte General Receive FIFO (GRF)
Accessed Through Microcontroller Interface
Supports Asynchronous and Isochronous
Receive.
2-Kbyte Asynchronous Transmit FIFO (ATF)
Accessed Through Microcontroller Interface
Supports Asynchronous Transmissions.
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Programmable Microcontroller Interface With
8-Bit or 16-Bit Data Bus, Multiple Modes of
Operation Including Burst Mode, and Clock
Frequency to 60 MHz
8-Bit or 16-Bit Data-Mover Port (DM Port)
Supports Isochronous, Asynchronous, and
Asynchronous Streaming Transmit/Receive
From an Unbuffered Port at a Clock
Frequency of 25 MHz.
Backward Compatible With All
TSB12LV31(GPLynx) Microcontroller and
Data-Mover Functionality in Hardware
Two-Channel Support for Isochronous
Receive to Unbuffered 8/16 Data-Mover Port
Four-Channel Support for Isochronous
Transmit From Unbufferred 8/16 Bit
Data-Mover Port
Single 3.3-V Supply Operation With 5-V
Tolerance Using 5-V Bias Terminals
High Performance 100-Pin PZ Package
NOTE:
Implements technology covered by one or more patents
of Apple Computer, Incorporated and SGS Thomson,
Limited.
DESCRIPTION
The TSB12LV32 (GP2Lynx) is a high-performance general-purpose IEEE 1394a-2000 link-layer controller (LLC)
with the capability of transferring data between the 1394 Phy-link interface, an external host controller, and an
external device connected to the data-mover port (local bus interface). The 1394 Phy-link interface provides the
connection to a 1394 physical layer device and is supported by the LLC. The LLC provides the control for
transmitting and receiving 1394 packet data between the microcontroller interface and the Phy-link interface via
internal 2-Kbyte FIFOs at rates up to 400 Mbps. The TSB12LV32 transmits and receives correctly formatted
1394 packets, generates and detects the 1394 cycle start packets, communicates transaction layer transmit
requests to the Phy, and generates and inspects the 32-bit cyclic redundancy check (CRC).
The TSB12LV32 is capable of being 1394 cycle master (CM), 1394 bus manager, 1394 isochronous resource
manager (IRM) if additional control status registers (CSRs) are added via the external host controller, and
supports reception of 1394 isochronous data on two channels and transmission of 1394 isochronous data on
four channels.
The TSB12LV32 supports a direct interface to many microprocessors/microcontrollers by including
programmable endian swapping. TSB12LV32 has a generic 16-/8-bit host bus interface which includes support
for a ColdFireE microcontroller mode at rates up to 60 MHz. The microcontroller interface can operate in byte or
word (16 bit) accesses.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
