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BB722

製品説明
仕様・特性

S i 5 3 0 / 5 31 REVISION D C R YS TA L O SCILLATOR (XO) (10 M H Z T O 1 . 4 GH Z ) Features  Si5602 Available with any-rate output  frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz  3rd generation DSPLL® with superior  jitter performance   3x better frequency stability than  SAW-based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout  Pb-free/RoHS-compliant Ordering Information: Applications See page 7.     SONET/SDH Networking  SD/HD video Test and measurement Clock and data recovery  FPGA/ASIC clock generation Pin Assignments: See page 6. Description The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si530/531 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si530/531 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si530/531 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. (Top View) NC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Si530 (LVDS/LVPECL/CML) V DD CLK– CLK+ 1 6 VDD NC Functional Block Diagram OE 2 5 NC GND 3 4 CLK Si530 (CMOS) 1 6 VDD NC 2 5 CLK– GND Fixed Frequency XO OE Any-rate 10–1400 MHz DSPLL® Clock Synthesis 3 4 CLK+ Si531 (LVDS/LVPECL/CML) OE Rev. 1.2 5/11 GND Copyright © 2011 by Silicon Laboratories Si530/531

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