3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
Features
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IDT71V124SA/HSA
Description
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
– Commercial: 10/12/15/20ns
– Industrial: 10/12/15/20ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 9ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
Functional Block Diagram
A0
•
•
•
ADDRESS
•
•
•
1,048,576-BIT
MEMORY ARRAY
DECODER
A16
8
I/O0 - I/O7
8
I/O CONTROL
.
8
WE
OE
CS
CONTROL
LOGIC
3873 drw 01
OCTOBER 2008
1
©2007- Integrated Device Technology, Inc.
DSC-3873/09
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics(1, 2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71V124SA10
Symbol
Parameter
71V124SA12
71V124SA15
71V124SA20
Com'l
Ind
Com'l
Ind
Com'l
Ind
Com'l
Ind
Unit
ICC
Dynamic Operating Current
CS < VLC, Outputs Open, VDD = Max., f = fMAX(3)
145
150
130
140
100
120
95
115
mA
ISB
Dynamic Standby Power Supply Current
CS > VHC, Outputs Open, VDD = Max., f = fMAX(3)
45
50
40
40
35
40
30
35
mA
ISB1
Full Standby Power Supply Current (static)
CS > VHC, Outputs Open, VDD = Max., f = 0(3)
10
10
10
10
10
10
10
10
mA
3873 tbl 06
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD–0.2V (High).
3. fMAX = 1/t RC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
AC Test Conditions
GND to 3.0V
Input Pulse Levels
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
1.5V
Output Reference Levels
See Figure 1 and 2
AC Test Load
3873 tbl 07
3.3V
320Ω
+1.5V
DATAOUT
50Ω
I/O
5pF*
Z0 = 50Ω
350Ω
30pF
3873 drw 03
.
3873 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t CLZ, tOLZ, tCHZ, tOHZ , tOW, and tWHZ)
3
6.42
