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部品型式

M5M51008DFP-70HI

製品説明
仕様・特性

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 Ver. 1.1 MITSUBISHI LSIs M5M51008DFP,VP,RV,KV -55HI, -70HI 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM FUNCTION The operation mode of the M5M51008D series are determined by a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S 1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H). When setting S1 at a high level or S 2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as I CC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode. FUNCTION TABLE S1 X H L L L S2 L X H H H W X X L H H Mode DQ OE X Non selection High-impedance X Non selection High-impedance Din X Write Dout L Read High-impedance H ICC Stand-by Stand-by Active Active Active Note 1: "H" and "L" in this table mean VIH and VIL, respectively. 2: "X" in this table should be "H" or "L". BLOCK DIAGRAM * * 9 A2 10 A5 A6 7 6 21 18 15 14 A7 5 13 A12 4 12 A14 3 11 A16 2 10 A15 31 4 A8 27 18 DQ5 27 19 DQ6 20 DQ7 21 DQ8 WRITE 29 W CONTROL INPUT DATA INPUTS/ OUTPUTS 2 A11 25 17 DQ4 26 3 A9 26 15 DQ3 25 7 A13 28 14 DQ2 29 131072 WORDS X 8 BITS (512 ROWS X128 COLUMNS X 16BLOCKS) 23 28 17 13 DQ1 22 5 A3 1 ADDRESS INPUTS CLOCK GENERATOR 8 16 30 22 S1 A1 11 19 6 30 S2 32 OUTPUT 24 OE ENABLE INPUT 8 32 VCC 24 16 GND (0V) A4 A0 12 20 A10 23 31 CHIP SELECT INPUTS * Pin numbers inside dotted line show those of TSOP 2

ブランド

RENESAS

会社名

ルネサス エレクトロニクス株式会社

本社国名

日本

事業概要

2010年(平成22年)4月に設立された大手半導体メーカー。半導体製品の研究開発・製造・販売・サービス。主力製品は、マイコン(CISC、RISC)、パワーデバイス、アナログ&ミックスドシグナルIC、汎用IC、高周波デバイス、光半導体、車載用LSI、産業用LSI、メモリ、ASIC、USB ASSP、システムLSI

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