NTMS10P02R2
Power MOSFET
−10 Amps, −20 Volts
P−Channel Enhancement−Mode
Single SOIC−8 Package
Features
•
•
•
•
•
•
•
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http://onsemi.com
Ultra Low RDS(on)
Higher Efficiency Extending Battery Life
Logic Level Gate Drive
Miniature SOIC−8 Surface Mount Package
Diode Exhibits High Speed, Soft Recovery
Avalanche Energy Specified
SOIC−8 Mounting Information Provided
Pb−Free Package is Available
−10 AMPERES
−20 VOLTS
14 mW @ VGS = −4.5 V
P−Channel
D
Applications
• Power Management in Portable and Battery−Powered Products,
G
i.e.: Cellular and Cordless Telephones and PCMCIA Cards
S
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−20
Vdc
Gate−to−Source Voltage − Continuous
VGS
"12
Vdc
RqJA
PD
ID
ID
PD
ID
IDM
50
2.5
−10
−8.0
0.6
−5.5
−50
°C/W
W
A
A
W
A
A
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
Pulsed Drain Current (Note 3)
RqJA
PD
ID
ID
PD
ID
IDM
80
1.6
−8.8
−6.4
0.4
−4.5
−44
°C/W
W
A
A
W
A
A
TJ, Tstg
−55 to
+150
°C
EAS
500
mJ
Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C
(VDD = −20 Vdc, VGS = −4.5 Vdc,
Peak IL = 5.0 Apk, L = 40 mH, RG = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
260
°C
March, 2006 − Rev. 3
1
D
D D
8
1
SOIC−8
CASE 751
STYLE 12
E10P02
AYWW G
G
1
S
S
S G
E10P02 = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NTMS10P02R2
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Mounted onto a 2″ square FR−4 Board
(1 in sq, Cu 0.06″ thick single sided), t = 10 seconds.
2. Mounted onto a 2″ square FR−4 Board
(1 in sq, Cu 0.06″ thick single sided), t = steady state.
3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2%.
© Semiconductor Components Industries, LLC, 2006
D
8
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
Pulsed Drain Current (Note 3)
Operating and Storage Temperature Range
MARKING DIAGRAM &
PIN ASSIGNMENT
NTMS10P02R2G
Package
Shipping†
SOIC−8
2500/Tape & Reel
SOIC−8
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTMS10P02R2/D
