MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators,
a voltage−controlled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCAin and
PCBin. Input PCAin can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self−bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1out, and maintains 90° phase shift at
the center frequency between PCAin and PCBin signals (both at 50%
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2out and LD, and maintains a 0°
phase shift between PCA in and PCB in signals (duty cycle is
immaterial). The linear VCO produces an output signal VCOout
whose frequency is determined by the voltage of input VCOin and the
capacitor and resistors connected to pins C1A, C1B, R1, and R2.
The source−follower output SFout with an external resistor is used
where the VCOin signal is needed but no loading can be tolerated.
The inhibit input Inh, when high, disables the VCO and source
follower to minimize standby power consumption. The zener diode
can be used to assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
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Buffered Outputs Compatible with Low−Power TTL
Diode Protection on All Inputs
Supply Voltage Range = 3.0 to 18 V
Pin−for−Pin Replacement for CD4046B
Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle
Limited
Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle
Limited
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
VDD
SOIC−16 WB
DW SUFFIX
CASE 751G
SOEIAJ−16
F SUFFIX
CASE 966
MARKING DIAGRAMS
16
16
14046BG
AWLYYWW
MC14046B
ALYWG
1
1
SOEIAJ−16
SOIC−16 WB
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range
VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
Value
−0.5 to +18.0
Input Voltage Range (All Inputs)
Unit
V
−0.5 to VDD + 0.5
DC Supply Voltage Range
Vin
http://onsemi.com
V
Iin
DC Input Current, per Pin
± 10
mA
PD
Power Dissipation, per Package (Note 1)
500
mW
TA
Operating Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 14
1
Publication Order Number:
MC14046B/D
