Part Number PPC405EP
Revision 1.08 – March 24, 2008
PPC405EP
Data Sheet
PowerPC 405EP Embedded Processor
Features
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AMCC PowerPC® 405 32-bit RISC processor
core operating up to 333MHz with 16KB Dand I-caches
PC-133 synchronous DRAM (SDRAM) interface
- 32-bit interface for non-ECC applications
4KB on-chip memory (OCM)
External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8- or 16-bit SRAM and
external peripherals
- Up to five devices
DMA support for memory and UARTs.
- Scatter-gather chaining supported
- Four channels
PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
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- Asynchronous PCI Bus interface
- Internal or external PCI Bus Arbiter
Two Ethernet 10/100Mbps (full-duplex) ports
with media independent interface (MII)
Programmable interrupt controller supports
seven external and 19 internal edge-triggered
or level-sensitive interrupts
Programmable timers
Software accessible event counters
Two serial ports (16750 compatible UART)
One IIC interface
General purpose I/O (GPIO) available
Supports JTAG for board level testing
Internal processor local bus (PLB) runs at
SDRAM interface frequency
Supports PowerPC processor boot from PCI
memory
Description
Designed specifically to address embedded
applications, the PowerPC 405EP (PPC405EP)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus interface,
AMCC
Ethernet interface, control for external ROM and
peripherals, DMA with scatter-gather support, serial
ports, IIC interface, and general purpose I/O.
Technology: CMOS SA-27E, 0.18 μm (0.11 μm Leff)
Package: 31mm, 385-ball, enhanced plastic ball grid
array (E-PBGA)
Power (typical): 0.72W at 266MHz
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