CY62177EV30 MoBL®
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Features
Functional Description
■
Thin small outline package (TSOP) I configurable as 2 M × 16
or as 4 M × 8 static RAM (SRAM)
■
Very high speed
❐ 55 ns
■
Wide voltage range
❐ 2.2 V to 3.7 V
■
Ultra low standby power
❐ Typical standby current: 3 A
❐ Maximum standby current: 25 A
■
Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE Features
The CY62177EV30 is a high performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
■
Automatic power down when deselected
■
Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 48-pin TSOP I package and 48-ball FBGA
package
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 11 for a complete
description of read and write modes.
Pin #13 of the 48 TSOP I package is an DNU pin that must be
left floating at all times to ensure proper application.
For a complete list of related resources, click here.
Logic Block Diagram
2M × 16
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BYTE
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
BHE
WE
CE2
CE1
OE
BLE
Power-Down
Circuit
Cypress Semiconductor Corporation
Document Number: 001-09880 Rev. *N
•
198 Champion Court
BHE
BLE
•
CE2
CE1
San Jose, CA 95134-1709
•
408-943-2600
Revised November 17, 2015
