NBSG14
2.5 V/3.3 V SiGe Differential
1:4 Clock/Data Driver with
RSECL* Outputs
*Reduced Swing ECL
http://onsemi.com
Description
The NBSG14 is a 1-to-4 clock/data distribution chip, optimized for
ultra-low skew and jitter.
Inputs incorporate internal 50 W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
All outputs loaded with 50 W to VCC − 2 V.
1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAMS*
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•
•
•
•
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•
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Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
RSECL Output Level (400 mV Peak-to-Peak Output),
Differential Output
50 W Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
These are Pb-Free Devices
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Features
16
1
SG
14
ALYWG
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 17
1
Publication Order Number:
NBSG14/D
