Section I. MAX II Device Family Data
Sheet
This section provides designers with the data sheet specifications for MAX® II devices.
The chapters contain feature definitions of the internal architecture, Joint Test Action
Group (JTAG) and in-system programmability (ISP) information, DC operating
conditions, AC timing parameters, and ordering information for MAX II devices.
This section includes the following chapters:
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Chapter 1, Introduction
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Chapter 2, MAX II Architecture
■
Chapter 3, JTAG and In-System Programmability
■
Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices
■
Chapter 5, DC and Switching Characteristics
■
Chapter 6, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the complete handbook.
© October 2008
Altera Corporation
MAX II Device Handbook
1. Introduction
MII51001-1.8
Introduction
The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-µm, 6-layermetal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210
equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices offer high
I/O counts, fast performance, and reliable fitting versus other CPLD architectures.
Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system
programmability (ISP), MAX II devices are designed to reduce cost and power while
providing programmable solutions for applications such as bus bridging, I/O
expansion, power-on reset (POR) and sequencing control, and device configuration
control.
Features
The MAX II CPLD has the following features:
■
■
Instant-on, non-volatile architecture
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Standby current as low as 29 µA
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Provides fast propagation delay and clock-to-output times
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Provides four global clocks with two clocks available per logic array block (LAB)
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UFM block up to 8 Kbits for non-volatile storage
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MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V
or 1.8 V
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MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
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Bus-friendly architecture including programmable slew rate, drive strength, bushold, and programmable pull-up resistors
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Schmitt triggers enabling noise tolerant inputs (programmable per pin)
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I/Os are fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 66 MHz
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Supports hot-socketing
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Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry
compliant with IEEE Std. 1149.1-1990
■
© October 2008
Low-cost, low-power CPLD
ISP circuitry compliant with IEEE Std. 1532
Altera Corporation
MAX II Device Handbook
