IDT7130SA/LA
IDT7140SA/LA
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Features
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High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
— Active: 550mW (typ.)
— Standby: 5mW (typ.)
– IDT7130/IDT7140LA
— Active: 550mW (typ.)
— Standby: 1mW (typ.)
MASTER IDT7130 easily expands data bus width to 16-ormore-bits using SLAVE IDT7140
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On-chip port arbitration logic (IDT7130 Only)
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
BUSYL
(1,2)
A9L
A0L
(1,2)
BUSYR
Address
Decoder
MEMORY
ARRAY
10
CEL
OEL
R/WL
Address
Decoder
A9R
A0R
10
ARBITRATION
and
INTERRUPT
LOGIC
CER
OER
R/WR
(2)
(2)
INTR
INTL
2689 drw 01
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
APRIL 2006
1
©2006 Integrated Device Technology, Inc.
DSC-2689/13
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