This part is not recommended for new designs
Use EZ-USB FX2LP instead of EZ-USB FX2 for new designs
CY7C68013
EZ-USB FX2™ USB Microcontroller
1.0
EZ-USB FX2 Features
• Single-chip integrated USB 2.0 Transceiver, SIE, and
Enhanced 8051 Microprocessor
• Software: 8051 code runs from:
— Internal RAM, which is downloaded via USB
— Internal RAM, which is loaded from EEPROM
— External memory device (128 pin package
• Four programmable BULK/INTERRUPT/
ISOCHRONOUS endpoints
— Buffering options: double, triple and quad
• 8- or 16-bit external data interface
• GPIF
• Supports bus-powered applications by using renumeration
• 3.3V operation
• Smart Serial Interface Engine
• Vectored USB interrupts
• Separate data buffers for the SETUP and DATA portions
of a CONTROL transfer
• Integrated I2C-compatible controller, runs at 100 or 400
kHz
• 48-MHz, 24-MHz, or 12-MHz 8051 operation
• Four integrated FIFOs
— Brings glue and FIFOs inside for lower system cost
— Automatic conversion to and from 16-bit buses
— Allows direct connection to most parallel interface
— Master or slave operation
— Programmable waveform descriptors and configuration registers to define waveforms
— FIFOs can use externally supplied clock or asynchronous strobes
— Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
• Integrated, industry standard enhanced 8051:
— Up to 48-MHz clock rate
— Four clocks per instruction cycle
— Two USARTS
— Easy interface to ASIC and DSP ICs
• Special autovectors for FIFO and GPIF interrupts
• Up to 40 general-purpose I/Os
• Four package options—128-pin TQFP, 100-pin TQFP,
56-pin QFN and 56-pin SSOP
• Four packages are defined for the family: 56 SSOP, 56
QFN, 100 TQFP, and 128 TQFP
— Three counter/timers
— Expanded interrupt system
— Two data pointers
High-performance micro
using standard tools
with lower-power options
VCC
x20
PLL
/0.5
/1.0
/2.0
Data (8)
Address (16)
FX2
8051 Core
12/24/48 MHz,
four clocks/cycle
1.5k
connected for
full speed
D+
D–
USB
2.0
XCVR
Integrated
full- and high-speed
XCVR
CY
Smart
USB
1.1/2.0
Engine
8.5 kB
RAM
I2C
Compatible
Master
Address (16) / Data Bus (8)
24-MHz
Ext. XTAL
ADDR (9)
GPIF
RDY (6)
CTL (6)
4 kB
FIFO
Enhanced USB core
Simplifies 8051 core
Abundant I/O
including two USARTS
Additional I/Os (24)
“Soft Configuration”
Easy firmware changes
8/16
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Up to 96 MBytes/s
burst rate
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08012 Rev. *F
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 25, 2005
