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M40SZ100WMQ6F
M40SZ100W 3 V NVRAM supervisor for LPSRAM Datasheet - production data Description The M40SZ100W NVRAM controller is a selfcontained device which converts a standard lowpower SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. 16 1 SO16 Features Convert low power SRAMs into NVRAMs 3 V operating voltage Precision power monitoring and power switching circuitry When an invalid VCC condition occurs, the conditioned chip enable output (ECON) is forced inactive to write protect the stored data in the SRAM. During a power failure, the SRAM is switched from the VCC pin to the external battery to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write-protected until a valid power condition returns. Automatic write-protection when VCC is out-oftolerance Choice of supply voltage and power-fail deselect voltage: – VCC = 2.7 to 3.6 V; 2.55 V VPFD 2.70 V Reset output (RST) for power on reset 1.25 V reference (for PFI/PFO) Less than 15 ns chip enable access propagation delay Battery low pin (BL) RoHS compliant – Lead-free second level interconnect December 2013 This is information on a product in full production. DocID007528 Rev 4 1/20 www.st.com
STM
STMicroelectronics NV
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