GS9091B
GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI
Key Features
Description
•
SMPTE 259M-C compliant descrambling and NRZI to
NRZ decoding (with bypass)
•
DVB-ASI 8b/10b decoding
The GS9091B is a 270Mb/s equalizing and reclocking deserializer with an internal FIFO. It provides a complete receive solution for SD-SDI and DVB-ASI applications.
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Integrated Cable Equalizer
•
500m typical equalization of Belden 1694A cable
•
Integrated line-based FIFO for data alignment/delay,
clock phase interchange, DVB-ASI data packet
extraction and clock rate interchange, and ancillary
data packet extraction
•
Integrated VCO and reclocker
•
User selectable additional processing features
including:
TRS, ANC data checksum, and EDH CRC error
detection and correction
programmable ANC data detection
illegal code remapping
•
Internal flywheel for noise immune H, V, F extraction
•
Automatic standards detection and indication
•
Enhanced Gennum Serial Peripheral Interface (GSPI)
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JTAG test interface
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Polarity insensitive for DVB-ASI and SMPTE signals
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+1.8V core power supply with optional +1.8V or +3.3V
I/O power supply
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Small footprint (11mm x 11mm)
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Low power operation (typically 350mW)
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Pb-free and RoHS compliant
Applications
•
SMPTE 259M-C Serial Digital Interfaces
•
DVB-ASI Serial Digital Interfaces
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Final Data Sheet
38910 - 3
February 2013
In addition to equalizing, reclocking and deserializing the
input data stream, the GS9091B performs NRZI -to-NRZ decoding, descrambling as per SMPTE 259M-C, and word
alignment when operating in SMPTE mode. When operating in DVB-ASI mode, the device will word align the data to
K28.5 sync characters and 8b/10b decode the received
stream.
The integrated equalizer is optimized for 270Mb/s and can
typically equalize up to 500m of Belden 1694A cable. Both
the equalizer and the internal reclocker are fully compatible with both SMPTE and DVB-ASI input streams.
The GS9091B includes a range of data processing functions
such as EDH support (error detection and handling), and
automatic standards detection. The device can also detect
and extract SMPTE 352M payload identifier packets and independently identify the received video standard. This information is read from internal registers via the host
interface port.
The GS9091B also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to carry out tasks such as data alignment / delay, clock phase interchange, MPEG packet extraction and clock rate
interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal operating at 27MHz.
The device may also be used in a low-latency data pass
through mode where only descrambling and word alignment will be performed in SMPTE mode.
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