Advance v0.6
®
ProASIC®3 nano Flash FPGAs
Features and Benefits
Advanced I/Os
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA Contents
Low Power
•
•
•
•
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
†
Clock Conditioning Circuit (CCC) and PLL
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
Low-Power ProASIC3 nano Products
1.5 V Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18 organization)†
High-Performance Routing Hierarchy
Enhanced Commercial Temperature Range
• Segmented, Hierarchical Routing and Clock Structure
• –20°C to +70°C
Table 1 • ProASIC3 nano Devices
ProASIC3 nano Devices
System Gates
A3PN010
A3PN015
A3PN020
A3PN030 1
A3PN060
A3PN125
A3PN250
10 k
15 k
20 k
30 k
60 k
125 k
250 k
Typical Equivalent Macrocells
86
128
172
256
512
1,024
2,048
VersaTiles (D-flip-flops)
260
384
520
768
1,536
3,072
6,144
2
RAM kbits (1,024 bits)
–
–
–
–
18
36
36
4,608-Bit Blocks2
–
–
–
–
4
8
8
1k
1k
1k
1k
1k
1k
1k
FlashROM Bits
Secure (AES) ISP
2
–
–
–
–
Yes
Yes
Yes
Integrated PLL in CCCs2
–
–
–
–
1
1
1
VersaNet Globals
4
4
4
6
18
18
18
I/O Banks
2
3
3
2
2
2
4
Maximum User I/Os (packaged device)
34
49
49
77
71
71
68
Maximum User I/Os (Known Good Die)
34
–
52
83
71
71
68
QN48
QN68
QN68
QN48, QN68
VQ100
VQ100
VQ100
VQ100
Package Pins
QFN
VQFP
Notes:
1. A3PN030 is available in the Z feature grade only.
2. A3PN030 and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E handbooks.
† A3PN030 and smaller devices do not support this feature.
January 2010
© 2010 Actel Corporation
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