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74F193PC
54F 74F193 Up Down Binary Counter with Separate Up Down Clocks General Description Commercial Individual preset inputs allow the circuit to be used as a programmable counter Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks Features Y Guaranteed 4000V minimum ESD protection e The ’F193 is an up down modulo-16 binary counter Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic thus simplifying multi-stage counter designs Package Number Military N16E 16-Lead (0 300 Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line M16A 16-Lead (0 150 Wide) Molded Small Outline JEDEC et 74F193PC Package Description 54F193DM (Note 2) 74F193SC (Note 1) M16D 16-Lead (0 300 Wide) Molded Small Outline EIAJ 54F193FM (Note 2) W16A 16-Lead Cerpack 54F193LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier Type C bs ol 74F193SJ (Note 1) Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9497–1 O IEEE IEC TL F 9497 – 2 TL F 9497 – 3 TL F 9497–4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9497 RRD-B30M75 Printed in U S A 54F 74F193 Up Down Binary Counter with Separate Up Down Clocks November 1994
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