www.fairchildsemi.com
FAN6555
2A DDR Bus Termination Regulator
Features
Description
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The FAN6555 switching regulator is designed to convert
voltage supplies ranging from 2.3V to 4V into a desired output voltage or termination voltage for DDR SDRAM memory. The FAN6555 can be implemented to produce regulated
output voltages in two different modes. In the default mode,
when the VREF pin is open, the FAN6555 output voltage is
50% of the voltage applied to VCCQ. The FAN6555 can also
be used to produce various user-defined voltages by forcing a
voltage on the VREFIN pin. In this case, the output voltage
follows the input VREFIN voltage. The switching regulator
is capable of sourcing or sinking up to 2A of current while
regulating an output VTT voltage to within 3% or less.
Transient output currents of ±3A can also be accommodated.
Can source and sink up to 2A continous, 3A peak
No heatsink required
Integrated Power MOSFETs
Generates termination voltages for DDR SDRAM
VREF input available for external voltage divider
Separate voltages for VCCQ and PVDD
Buffered VREF output
VOUT of ±3% or less at 2A
Minimum external components
16-pin SOIC package
-40°C to +85°C operating temperature range
Shutdown for standby or suspend mode operation
Thermal Shutdown ≈ 130ºC
The FAN6555 can also be used in conjunction with series
termination resisitors to provide an excellent voltage source
for active termination schemes of high speed transmission
lines as those seen in high speed memory buses and distributed backplane designs.
Block Diagram
15
VCCQ
16
AVCC
14
1
VREFOUT
9
VDD
12
VDD
SHDN
2
7
PVDD1
PVDD2
VL1
(VOUT)
OSCILLATOR/
RAMP
GENERATOR
3
–
200kΩ
S
+
VREF BUFFER
Q
6
VL2
(VOUT)
–
R
Q
+
VREFIN
11
+
200kΩ
AGND
–
ERROR AMP
RAMP
COMPARATOR
13
VFB
10
DGND
8
PGND1
4
PGND2
5
REV. 1.1.3 8/4/03
