August 1997
FDC6303N
Digital FET, Dual N-Channel
General Description
Features
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. This device has been designed especially for
low voltage applications as a replacement for digital
transistors in load switching applications. Since bias
resistors are not required this one N-Channel FET can
replace several digital transistors with different bias
resistors like the IMHxA series.
SOT-23
25 V, 0.68 A continuous, 2 A Peak.
RDS(ON) = 0.6 Ω @ VGS = 2.7 V
RDS(ON) = 0.45 Ω @ VGS= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple NPN digital transistors (IMHxA series)
with one DMOS FET.
SuperSOTTM-8
SuperSOTTM-6
SO-8
SOT-223
SOIC-16
Mark: .303
4
5
2
6
Absolute Maximum Ratings
3
1
T A = 25°C unless otherwise noted
Symbol
Parameter
FDC6303N
Units
VDSS
Drain-Source Voltage
25
V
VGSS
Gate-Source Voltage
8
V
ID
Drain Current
0.68
A
- Continuous
- Pulsed
PD
Maximum Power Dissipation
2
(Note 1a)
(Note 1b)
TJ,TSTG
Operating and Storage Temperature Range
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
0.9
W
0.7
-55 to 150
°C
6.0
kV
(Note 1a)
140
°C/W
(Note 1)
60
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
© 1997 Fairchild Semiconductor Corporation
FDC6303N Rev.C
