288Mb: x18 SIO RLDRAM 2
Features
SIO RLDRAM 2
MT49H16M18C – 16 Meg x 18 x 8 banks
MT49H64M9C – 64 Meg x 9 x 8 banks
Features
Options
• Clock cycle timing
– 1.875ns @ tRC = 15ns
– 2.5ns @ tRC = 15ns
– 2.5ns @ tRC = 20ns
– 3.3ns @ tRC = 20ns
• Configuration
– 16 Meg x 18
• Operating temperature range
– Commercial (0° to +95°C)
– Industrial (TC = –40°C to +95°C; T A =
–40°C to +85°C)
• Package
– 144-ball μBGA
– 144-ball μBGA (Pb-free)
– 144-ball FBGA
– 144-ball FBGA (Pb-free)
• Revision
• 533 MHz DDR operation (1.067 Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
• Organization
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– 16 Meg x 18 separate I/O
– 8 banks
Cyclic bank switching for maximum bandwidth
Reduced cycle time (15ns at 533 MHz)
Nonmultiplexed addresses (address multiplexing
option available)
SRAM-type interface
Programmable READ latency (RL), row cycle time,
and burst sequence length
Balanced READ and WRITE latencies in order to optimize data bus utilization
Data mask for WRITE commands
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
output data clock signals
Data valid signal (QVLD)
32ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32ms)
HSTL I/O (1.5V or 1.8V nominal)
–Ω matched impedance outputs
2.5V V EXT, 1.8V V DD, 1.5V or 1.8V V DDQ I/O
On-die termination (ODT) RTT
PDF: 09005aef80a41b59
288Mb_RLDRAM_2_SIO.pdf - Rev. I 6/15 EN
1
Note:
1
Marking
-18
-25E
-25
-33
16M18
None
IT
FM
BM
TR
SJ
:B
1. Not all options listed can be combined to
define an offered product. Use the part catalog search on micron.com for available offerings.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
