CY8C29466/CY8C29566
CY8C29666/CY8C29866
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
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❐
❐
Powerful Harvard-architecture processor
❐ M8C processor speeds to 24 MHz
❐ Two 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 3.0 V to 5.25 V
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Industrial temperature range: –40 °C to +85 °C
Four 40 mA analog outputs on GPIOs
Configurable interrupt on all GPIOs
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Additional system resources
2
❐ I C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
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Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and
programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
❐ Complex events
❐ C compilers, assembler, and linker
(PSoC®
Advanced peripherals
blocks)
❐ 12 rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐ 16 digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Up to four full-duplex universal asynchronous receiver
transmitters (UARTs)
• Multiple serial peripheral interface (SPI) masters or slaves
• Can connect to all general-purpose I/O (GPIO) pins
❐ Create complex peripherals by combining blocks
Logic Block Diagram
Port
7
Port
6
Port
5
Port
4
Port
3
Port
2
Port
1
Port 0 with
Analog Drivers
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
2 KB
Precision, programmable clocking
[1] 24- / 48-MHz main oscillator
❐ Internal ±5%
❐ 24- / 48-MHz with optional 32.768 kHz crystal
❐ Optional external oscillator, up to 24 MHz
❐ Internal oscillator for watchdog and sleep
Global Analog Interconnect
SROM
Flash 32KB
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Flexible on-chip memory
❐ 32 KB flash program storage 50,000 erase/write cycles
❐ 2 KB static random access memory (SRAM) data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ Electrically erasable programmable read-only memory
(EEPROM) emulation in flash
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Programmable pin configurations
❐ 25-mA sink, 10-mA source on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐ Eight standard analog inputs on GPIOs, plus four additional
analog inputs with restricted routing
Digital
Clocks
Multiply
Accum.
Analog
Block
Array
Analog
Input
Muxing
POR and LVD
Decimator
I2 C
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Errata: For information on silicon errata, see “Errata” on page 63. Details include trigger conditions, devices affected, and proposed workaround.
Note
1. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see Errata on page 63.
Cypress Semiconductor Corporation
Document Number: 38-12013 Rev. AC
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 19, 2017
