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MT29C4G48MAPLCJI-6IT
Preliminary‡ 168-Ball NAND Flash and LPDRAM PoP (TI OMAP) MCP Features NAND Flash and Mobile LPDRAM 168-Ball Package-on-Package (PoP) MCP Combination Memory (TI OMAP™) MT29CxGxxMAxxxxx Features Figure 1: PoP Block Diagram Micron® NAND Flash and LPDRAM components RoHS-compliant, “green” package Separate NAND Flash and LPDRAM interfaces Space-saving multichip package/package-on-package combination • Low-voltage operation (1.70–1.95V) • Industrial temperature range: –40°C to +85°C • • • • NAND Flash Device NAND Flash Power NAND Flash Interface NAND Flash-Specific Features Organization • Page size – x8: 2112 bytes (2048 + 64 bytes) – x16: 1056 words (1024 + 32 words) • Block size: 64 pages (128K + 4K bytes) LPDRAM Power LPDRAM Device LPDRAM Interface Mobile LPDRAM-Specific Features • • • • • • • • No external voltage reference required No minimum clock rate requirement 1.8V LVCMOS-compatible inputs Programmable burst lengths Partial-array self refresh (PASR) Deep power-down (DPD) mode Selectable output drive strength STATUS REGISTER READ (SRR) supported1 Options2 • Mobile LPDRAM – 200 MHz CL33 – 166 MHz CL3 – 133 MHz CL3 Notes: PDF: 09005aef83070ff3 168ball_nand_lpdram_j4xx_omap.pdf - Rev. I 6/09 1 Marking -5 -6 -75 1. Contact factory for remapped SRR output. 2. For part numbering and physical part markings, see Figure 2 (page 2) and Table 1 (page 3). 3. CL = CAS (READ) latency. Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
MICRON
Micron Technology
U.S.A
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