NTD2955, NVD2955
Power MOSFET
−60 V, −12 A, P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low−voltage, high−
speed switching applications in power supplies, converters, and power
motor controls. These devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer an additional safety margin against unexpected
voltage transients.
www.onsemi.com
V(BR)DSS
RDS(on) TYP
ID MAX
−60 V
155 mW @ −10 V, 6 A
−12 A
D
Features
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Designed for Low−Voltage, High−Speed Switching Applications and
P−Channel
G
to Withstand High Energy in the Avalanche and Commutation Modes
• NVD and SVD Prefix for Automotive and Other Applications
4
4
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
1
1 2
Symbol
Value
Unit
3
Drain−to−Source Voltage
VDSS
−60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 25
Vdc
Vpk
DPAK
CASE 369C
STYLE 2
ID
IDM
−12
−18
Adc
Apk
Rating
Drain Current
Dr− Continuous @ Ta = 25°C
Dr− Single Pulse (tp ≤ 10 ms)
PD
55
TJ, Tstg
−55 to
175
°C
EAS
216
mJ
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
W
Operating and Storage Temperature
Range
3
IPAK
CASE 369D
STYLE 2
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 12 Apk, L = 3.0 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8 in. from case for
10 seconds
AYWW
NT
2955G
Total Power Dissipation @ Ta = 25°C
2
AYWW
NT
2955G
•
S
Requiring Unique Site and Control Change Requirements;
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
2
1
3
Drain
Gate
Source
RqJC
RqJA
RqJA
2.73
71.4
100
°C/W
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 1 in pad size
(Cu area = 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size (Cu area = 0.412 in2).
A
NT2955/NV2955
NT2955
Y
WW
G
1 2 3
Gate Drain Source
= Assembly Location*
= Specific Device Code (DPAK)
= Specific Device Code (IPAK)
= Year
= Work Week
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2017
March, 2017 − Rev. 16
1
Publication Order Number:
NTD2955/D