512Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
MT48LC128M4A2 – 32 MEG x 4 x 4 BANKS
MT48LC64M8A2 – 16 MEG x 8 x 4 BANKS
MT48LC32M16A2 – 8 MEG x 16 x 4 BANKS
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
Features
Figure 1: Pin Assignment (Top View)
54-Pin TSOP
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
x4 x8 x16
-
NC DQ0
-
-
NC NC
DQ0 DQ1
-
-
NC NC
NC DQ2
-
-
NC NC
DQ1 DQ3
-
-
NC
NC
-
NC
-
128M4
64M8
32M16
-
NC
MARKING
• Configurations
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• WRITE Recovery (tWR)
t
WR = “2 CLK”1
• Plastic Package - OCPL2
54-pin TSOP II (400 mil)
54-pin TSOP II (400 mil) Lead-Free
• Timing (Cycle Time)
7.5ns @ CL = 2 (PC133)
7.5ns @ CL = 3 (PC133)
• Self Refresh
Standard
Low-power
• Operating Temperature
Commercial (0oC to +70oC)
Industrial Temperature
(40oC +85oC)
-
-
x16 x8 x4
VDD
DQ0
VDDQ
DQ1
DQ2
VssQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VssQ
DQ7
VDD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Vss
DQ15 DQ7
VssQ DQ14 NC
DQ13 DQ6
VDDQ DQ12 NC
DQ11 DQ5
VssQ DQ10 NC
DQ9 DQ4
VDDQ DQ8 NC
Vss
NC
DQMH DQM
CLK
CKE A12 A11 A9
A8
A7
A6
A5
A4
Vss
-
NC
NC
DQ3
NC
NC
NC
DQ2
NC
DQM
-
A2
TG
P
NOTE:
-7E
-75
The # symbol indicates signal is active LOW. A
dash (-) indicates x8 and x4 pin function is
same as x16 pin function.
Configuration
32 Meg x 4 x 4
banks
16 Meg x 8 x
4 banks
8 Meg x 16 x 4
banks
Refresh Count
8K
8K
8K
Row Addressing
None
L
8K (A0-A12)
8K (A0-A12)
8K (A0-A12)
Bank Addressing
None
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
Column
Addressing
4K (A0-A9,
A11, A12)
2K (A0-A9,
A11)
1K (A0-A9)
IT3
Key Timing Parameters
Part Number Example:
MT48LC32M16A2TG-75
NOTE:
ACCESS TIME
SPEED
GRADE
2. Off-center parting line.
3. Contact factory for availability.
09005aef80818a4a
512mbSDRAMfront.fm - Rev. G 1/04 EN
1
CL = 2*
CL = 3*
SETUP
TIME
HOLD
TIME
-7E
-75
-7E
-75
1. Refer to Micron Technical Note TN-48-05.
CLOCK
FREQUENCY
143 MHz
133 MHz
133 MHz
100 MHz
–
–
5.4ns
6ns
5.4ns
5.4ns
-
1.5ns
1.5ns
1.5ns
1.5ns
0.8ns
0.8ns
0.8ns
0.8ns
©2000 Micron Technology, Inc. All rights reserved.
