THC63LVDR84B_Rev.2.2_E
THC63LVDR84B
LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER (Rising Edge Clock)
General Description
Features
The THC63LVDR84B receiver supports wide VCC
r a n g e ( 2 . 5 ~ 3 . 6 V ) . A t s i n g l e 2 . 5 V s u p p l y, t h e
THC63LVDR84B reduces EMI and power consumption.
The THC63LVDR84B receiver convert the four
LVDS(Low Voltage Differential Signaling) data streams
back into 24bits of CMOS/TTL data with rising edge
clock.
At a transmit clock frequency of 85MHz, 24bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 2.3Gbps.
• Wide dot clock and Wide VCC range:
Clock Frequency[MHz]
15 to 20 20 to 70 70 to 85
to 2.7
n/a
available
n/a
to 3.0 available available
n/a
to 3.6 available available available
: not available
VCC[V]
2.5
2.7
3.0
n/a
• Rising Edge Clock
• PLL requires No external components
• Rx power consumption < 80mW @VCC 2.5V,
•
•
•
65MHz Grayscale
Power-Down Mode
Low profile 56 Lead TSSOP Package
Pin compatible with DS90CR286ATMD
Block Diagram
THC63LVDR84B
RA +/-
DATA
(LVDS)
RB +/RC +/RD +/-
CLOCK
(LVDS) RCLK +/15 to 85MHz
LVDS TO TTL PARALLEL
CMOS/TTL
OUTPUT
PLL
7 RA0-6
7
7
RB0-6
RC0-6
7 RD0-6
RECEIVER
CLOCK OUT
(15 to 85MHz)
/PDWN
(105-595Mbit/On Each LVDS Channel)
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.
