CY7C1061DV33
16-Mbit (1 M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
Functional Description
■
High speed
❐ tAA = 10 ns
The CY7C1061DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
■
Low active power
❐ ICC = 175 mA at 100 MHz
■
Low CMOS standby power
❐ ISB2 = 25 mA
■
Operating voltages of 3.3 ± 0.3 V
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A19). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A19).
■
2.0 V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
■
Easy memory expansion with CE1 and CE2 features
■
Available in Pb-free 54-pin TSOP II and 48-ball VFBGA
packages
■
Offered in single CE and dual CE options
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 12
for a complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH, and WE LOW).
The CY7C1061DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and 48-ball
VFBGA packages.
For a complete list of related documentation, click here.
Logic Block Diagram
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
1M x 16
ARRAY
I/O0 – I/O7
I/O8 – I/O15
A10
A11
A 12
A 13
A 14
A15
A16
A17
A18
A19
COLUMN
DECODER
BHE
WE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05476 Rev. *J
•
198 Champion Court
•
CE2
CE1
San Jose, CA 95134-1709
•
408-943-2600
Revised October 27, 2015
