CY7C4421V/4201V/4211V/4221VCY7C4231V/4241V/4251VLow-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Featuresb
• Space saving 32-pin 7 mm × 7 mm TQFP
• 32-pin PLCC
• High-speed, low-power, first-in, first-out (FIFO)
memories
• Available in Pb-Free Packages
• 64 x 9 (CY7C4421V)
Functional Description
• 256 x 9 (CY7C4201V)
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty
flags. These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
• 512 x 9 (CY7C4211V)
• 1K x 9 (CY7C4221V)
• 2K x 9 (CY7C4231V)
• 4K x 9 (CY7C4241V)
• 8K x 9 (CY7C4251V)
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
• High-speed 66-MHz operation (15-ns read/write cycle
time)
• Low power (ICC = 20 mA)
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• 5V-tolerant inputs VIH max = 5V
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a Free-Running Read Clock (RCLK) and
two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock
frequencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
• Width expansion capability
Logic Block Diagram
Pin Configuration
D0 − 8
D2
D3
D4
D5
D6
D7
D8
PLCC
Top View
INPUT
REGISTER
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FLAG
LOGIC
Dual Port
RAM Array
64 x 9
WRITE
POINTER
RS
EF
PAE
PAF
FF
4 3 2 1 32 3130
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12
22
21
13
14151617181920
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
EF
FF
Q0
Q1
Q2
Q3
Q4
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
READ
POINTER
8Kx 9
RESET
LOGIC
THREE-ST
ATE
OUTPUTREGISTER
READ
CONTROL
OE
Q0 − 8
Cypress Semiconductor Corporation
Document #: 38-06010 Rev. *B
•
RCLK REN1 REN2
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 14, 2005
