SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001
D
D
D
D
D
D
D
D
D
D
D
Eight Line Receivers Meet or Exceed the
Requirements of ANSI TIA/EIA-644
Standard
Integrated 110-Ω Line Termination
Resistors on LVDT Products
Designed for Signaling Rates† Up To
630 Mbps
SN65 Version’s Bus-Terminal ESD Exceeds
15 kV
Operates From a Single 3.3-V Supply
Propagation Delay Time of 2.6 ns (Typ)
Output Skew 100 ps (Typ)
Part-To-Part Skew Is Less Than 1 ns
LVTTL Levels Are 5-V Tolerant
Open-Circuit Fail Safe
Flow-Through Pin Out
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
NOT RECOMMENDED FOR NEW DESIGNS
For Replacement Use ’LVDx388A
’LVDS388, ’LVDT388
DBT PACKAGE
(TOP VIEW)
A1A
A1B
A2A
A2B
NC
B1A
B1B
B2A
B2B
NC
C1A
C1B
C2A
C2B
NC
D1A
D1B
D2A
D2B
description
The ‘LVDS388 and ‘LVDT388 (T designates
integrated termination) are eight differential line
receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3-V
supply rail. Any of the eight differential receivers
will provide a valid logical output state with a
+100-mV differential input voltage within the input
common-mode voltage range. The input
common-mode voltage range allows 1 V of
ground potential difference between two LVDS
nodes. Additionally, the high-speed switching of
LVDS signals always require the use of a line
impedance matching resistor at the receiving end
of the cable or transmission media. The LVDT
product eliminates this external resistor by
integrating it with the receiver.
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
GND
VCC
ENA
A1Y
A2Y
ENB
B1Y
B2Y
GND
VCC
GND
C1Y
C2Y
ENC
D1Y
D2Y
END
VCC
GND
logic diagram (positive logic)
’LVDx388
’LVDT388 ONLY
1A
1Y
1B
EN
2A
2Y
2B
(1/4 of ’LVDx388 shown)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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