PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5132AABG (16M words × 32 bits)
Features
• Density: 512M bits
• Organization
4M words × 32 bits × 4 banks
• Package
128-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate
800Mbps/667Mbps (max.)
• 2KB page size
Row address: A0 to A12
Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Driver strength: normal, weak, 1/4
• Refresh: auto-refresh, self-refresh
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• /DQS can be disabled for single-ended Data Strobe
operation
L
EO
Specifications
Pr
• Refresh cycles: 8192 cycles/64ms
t
uc
od
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Document No. E1115E40 (Ver. 4.0)
Date Published July 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2010.
Elpida Memory, Inc. 2007-2008
